Integrated semiconductor memory circuits, particularly those employing cells which include essentially a storage capacitor and a switch, have achieved high memory cell densities. One of the simplest circuits for providing small memory cells is described in commonly assigned U.S. Pat. No. 3,387,286, filed July 14, 1967, by R. H. Dennard. Each of these cells employs essentially only a storage capacitor and a field effect transistor acting as a switch to selectively connect the capacitor to a bit/sense line. In also commonly assigned U.S. Pat. Nos. 3,811,076 by W. M. Smith and 3,841,926 by R. R. Garnache and W. M. Smith, both filed Jan. 2, 1973, there is disclosed a one-device field effect transistor memory cell of the type described in the above-identified Dennard patent which is made to a small size by utilizing a layer of doped polycrystalline silicon separated by a dielectric medium disposed on the surface of a semiconductor substrate for forming a storage capacitor.
In another commonly assigned U.S. Pat. No. 4,080,590, filed Mar. 31, 1976, by W. D. Pricer, there is disclosed a merged charge memory produced in a unipolar technology which is provided with very small capacitor cells, each of which includes substantially only a small storage capacitor having a bit/sense line connected to one terminal of the capacitor and a word line providing a coupling to the other terminal of the capacitor. In an embodiment of that invention, a direct current source of charges is produced at the surface of a semiconductor substrate and a plurality of inversion storage capacitors are formed also at the surface of the semiconductor substrate in a spaced-apart relationship from the charge source. Voltage pulses representing binary digits are applied to one terminal of the capacitors and the other terminal of the capacitors is coupled to the direct source of charges by the application of a word pulse to a word line.
In yet another commonly assigned U.S. Pat. No. 4,040,017, filed Mar. 31, 1976, by H. S. Lee, there is disclosed a capacitor memory similar to that disclosed in the above-identified U.S. Pat. No. 4,080,590 wherein the charges are produced from a charge source in the form of pulses injected into the storage capacitors rather than by utilizing a direct current source of charges.
In commonly assigned U.S. patent application having Ser. No. 60,075, filed July 24, 1979 by S. N. Chakravarti et al there is disclosed a merged charge memory wherein the storage capacitor or cell includes a first plate made of doped polysilicon and a second plate has a floating conductive N diffusion region in a P-type substrate acting as a reservoir of electrons to provide increased signal strength.
In commonly assigned U.S. Pat. No. 4,160,275, filed on Apr. 3, 1978, by H. S. Lee, W. D. Pricer and N. G. Vogl, Jr., there is disclosed an accessing arrangement which is particularly suitable for a merged charge memory produced in unipolar technology of the type described hereinabove wherein the minimum pitch of a sense amplifier may be several times the dimension of the desired or optimum bit line pitch of a merged charge memory array by selecting at one time only a small number of cells, such as a byte, associated with a word line for writing or reading purposes.
In commonly assigned U.S. patent application having Ser. No. 134,259, filed Mar. 26, 1980, by W. D. Pricer, there is disclosed a sense amplifying system having first and second bit lines and first and second differential amplifiers arranged in tandem with a first isolation device connecting one side of the first amplifier to the first bit line and a second isolation device connecting the other side of the first amplifier to the second bit line and with a third isolation device connecting one side of the second amplifier to the first bit line and a fourth isolation device connecting the other side of the second amplifier to the second bit line. A precharging circuit charges the first and second lines to the same potential. The first amplifier is used to sense signals on the first line while using a reference voltage derived from the second line and the second amplifier is used to sense signals on the second line while using a reference voltage derived from the first word line.
IBM Technical Disclosure Bulletin Vol. 22 No. 7 December 1979 "One Device Dynamic Bipolar Memory with Dummy Cells" by J. E. Selleck discloses a reference level generation technique for a bipolar memory wherein the dummy signal is produced in a dummy cell which is made similar to that of the storage cells.
U.S. Pat. No. 3,909,631, filed Aug. 2, 1973, teaches a sensing technique for a one device FET memory which includes dummy cells having capacitors similar to those of the storage cells with the reference signal applied to the dummy cell capacitors being derived from voltages similar to those used to write ones and zeros in the memory. The reference voltage is provided by a circuit wherein ground is produced at one terminal and a high voltage is produced at a second terminal with these voltages being equalized by a transistor prior to being applied to the dummy cell capacitors.
In U.S. Pat. No. 3,678,473, filed June 4, 1970, the dummy cell capacitor has half the capacity of the storage cell capacitor.